SAI2_MCLK_DIR=SAI2_MCLK_DIR_0, SAI1_MCLK_DIR=SAI1_MCLK_DIR_0, ENET_TX_CLK_SEL=ENET_TX_CLK_SEL_0, GINT=GINT_0, SAI3_MCLK3_SEL=SAI3_MCLK3_SEL_0, EXC_MON=EXC_MON_0, SAI1_MCLK3_SEL=SAI1_MCLK3_SEL_0, SAI1_MCLK1_SEL=SAI1_MCLK1_SEL_0, SAI3_MCLK_DIR=SAI3_MCLK_DIR_0, CM7_FORCE_HCLK_EN=CM7_FORCE_HCLK_EN_0, ENET_REF_CLK_DIR=ENET_REF_CLK_DIR_0, SAI2_MCLK3_SEL=SAI2_MCLK3_SEL_0, SAI1_MCLK2_SEL=SAI1_MCLK2_SEL_0
GPR1 General Purpose Register
| SAI1_MCLK1_SEL | SAI1 MCLK1 source select 0 (SAI1_MCLK1_SEL_0): ccm.ssi1_clk_root 1 (SAI1_MCLK1_SEL_1): ccm.ssi2_clk_root 2 (SAI1_MCLK1_SEL_2): ccm.ssi3_clk_root 3 (SAI1_MCLK1_SEL_3): iomux.sai1_ipg_clk_sai_mclk 4 (SAI1_MCLK1_SEL_4): iomux.sai2_ipg_clk_sai_mclk 5 (SAI1_MCLK1_SEL_5): iomux.sai3_ipg_clk_sai_mclk |
| SAI1_MCLK2_SEL | SAI1 MCLK2 source select 0 (SAI1_MCLK2_SEL_0): ccm.ssi1_clk_root 1 (SAI1_MCLK2_SEL_1): ccm.ssi2_clk_root 2 (SAI1_MCLK2_SEL_2): ccm.ssi3_clk_root 3 (SAI1_MCLK2_SEL_3): iomux.sai1_ipg_clk_sai_mclk 4 (SAI1_MCLK2_SEL_4): iomux.sai2_ipg_clk_sai_mclk 5 (SAI1_MCLK2_SEL_5): iomux.sai3_ipg_clk_sai_mclk |
| SAI1_MCLK3_SEL | SAI1 MCLK3 source select 0 (SAI1_MCLK3_SEL_0): ccm.spdif0_clk_root 1 (SAI1_MCLK3_SEL_1): SPDIF_EXT_CLK 2 (SAI1_MCLK3_SEL_2): spdif.spdif_srclk 3 (SAI1_MCLK3_SEL_3): spdif.spdif_outclock |
| SAI2_MCLK3_SEL | SAI2 MCLK3 source select 0 (SAI2_MCLK3_SEL_0): ccm.spdif0_clk_root 1 (SAI2_MCLK3_SEL_1): SPDIF_EXT_CLK 2 (SAI2_MCLK3_SEL_2): spdif.spdif_srclk 3 (SAI2_MCLK3_SEL_3): spdif.spdif_outclock |
| SAI3_MCLK3_SEL | SAI3 MCLK3 source select 0 (SAI3_MCLK3_SEL_0): ccm.spdif0_clk_root 1 (SAI3_MCLK3_SEL_1): SPDIF_EXT_CLK 2 (SAI3_MCLK3_SEL_2): spdif.spdif_srclk 3 (SAI3_MCLK3_SEL_3): spdif.spdif_outclock |
| GINT | Global Interrupt 0 (GINT_0): Global interrupt request is not asserted 1 (GINT_1): Global interrupt request is asserted |
| ENET_TX_CLK_SEL | ENET_TX_CLK select 0 (ENET_TX_CLK_SEL_0): Do not use. 1 (ENET_TX_CLK_SEL_1): ENET_TX_CLK is the 25MHz MII clock. |
| ENET_REF_CLK_DIR | This bitfield controls the direction of ENET_REF_CLK. ENET_REF_CLK is the 50MHz RMII clock. 0 (ENET_REF_CLK_DIR_0): ENET_REF_CLK is input 1 (ENET_REF_CLK_DIR_1): ENET_REF_CLK is output driven by ref_enetpll0 |
| SAI1_MCLK_DIR | sai1.MCLK signal direction control 0 (SAI1_MCLK_DIR_0): sai1.MCLK is input signal 1 (SAI1_MCLK_DIR_1): sai1.MCLK is output signal |
| SAI2_MCLK_DIR | sai2.MCLK signal direction control 0 (SAI2_MCLK_DIR_0): sai2.MCLK is input signal 1 (SAI2_MCLK_DIR_1): sai2.MCLK is output signal |
| SAI3_MCLK_DIR | sai3.MCLK signal direction control 0 (SAI3_MCLK_DIR_0): sai3.MCLK is input signal 1 (SAI3_MCLK_DIR_1): sai3.MCLK is output signal |
| EXC_MON | Exclusive monitor response select of illegal command 0 (EXC_MON_0): OKAY response 1 (EXC_MON_1): SLVError response |
| CM7_FORCE_HCLK_EN | Arm CM7 platform AHB clock enable 0 (CM7_FORCE_HCLK_EN_0): AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible 1 (CM7_FORCE_HCLK_EN_1): AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible |